1. Field of the Invention: The invention relates to a system and method for testing semiconductor devices and, more particularly, to such a system and method in which when failures are detected, decision circuitry determines whether it is more efficient to retest or repair the semiconductor device.
2. State of the Art: Typically, finished integrated semiconductor device assemblies include a die or dice that is attached to a lead frame and encapsulated with an encapsulant. Numerous expensive and time-consuming steps are involved in producing such semiconductor device assemblies. These steps may include the following: (1) forming dice on a wafer substrate, (2) testing the dice, (3) cutting dice from the wafer, (4) connecting a die or dice to a lead frame, (5) encapsulating the die or dice, lead frame, connecting wires, and any auxiliary circuitry, (6) performing burn-in and/or providing other stresses to the dice, and (7) testing the semiconductor device assembly at various stages of processing.
In semiconductor manufacturing, typically, the term xe2x80x9cfront-endxe2x80x9d refers to the fabrication of semiconductor devices to the level of completed and tested wafers. The term xe2x80x9cbackendxe2x80x9d refers to production stages of semiconductor devices occurring after the front-end and including such semiconductor device production stages as packaging, burn-in, testing, sorting, marking, and environmental testing.
When tested, a semiconductor device may have some failure due to various causes including, but not limited to, an internal defect in the die or chip, a bad bonding connection, or a bad connection between a lead finger and a probe or other test device. Failures in a completed semiconductor device assembly can prevent it from operating as intended. In spite of painstaking attention to detail, failures may be introduced at various levels of production. For example, defects in forming the die may cause a failure. It has been found, however, that some defects are manifest immediately, while other defects are manifest only after the die has been operated for some period of time.
xe2x80x9cBurn-inxe2x80x9d refers to the process of accelerating failures that occur during the infant mortality phase of component life in order to remove the inherently weaker semiconductor devices. The process has been regarded as critical for product reliability since the semiconductor industry began. There have been two basic types of burn-in. During the process known as xe2x80x9cstaticxe2x80x9d burn-in, temperatures are increased (or sometimes decreased) while only some of the pins on a test semiconductor device are biased. No data is written to the semiconductor device, nor is the semiconductor device exercised under stress during static burn-in. During xe2x80x9cunmonitored dynamicxe2x80x9d bum-in of a semiconductor device, temperatures are increased while the pins on the semiconductor device being tested are biased.
In recent years, as semiconductor device systems have grown in complexity, the need for more and more reliable components has escalated. This need has been met in two ways. First, in semiconductor device manufacturing processes where the manufacturing process technology has reached a level of maturity and stability, inherent manufacturing defects in the semiconductor device caused by contamination and process variation have been reduced. As a result, latent failures in the semiconductor device have been significantly reduced, resulting in lower field or usage failure rates. Further, more sophisticated methods of screening infant mortality failures in semiconductor devices have been developed to help minimize such failures.
To address these issues, an xe2x80x9cintelligentxe2x80x9d burn-in approach of the semiconductor device can be utilized. The term xe2x80x9cintelligent burn-inxe2x80x9d, as used in this discussion, refers to the ability to combine functional, programmable testing with the traditional burn-in cycling of the semiconductor device under test while the semiconductor device is located in the same chamber.
Some semiconductor devices have internal test modes not accessible during normal operation. These test modes may be invoked on automatic test equipment (ATE) by applying a high voltage to a single pin. The semiconductor device is then addressed in a manner so as to specify the operating mode of interest. Operating modes, such as data compression, grounded substrate, and cell plate biasing can be enabled, thus allowing evaluation of operating characteristics of the semiconductor device and help in isolating possible failure mechanisms.
The electrical characterization data gathered from such tests is then used to identify the part of the circuit of the semiconductor device that appears to be malfunctioning, the possible location(s) of such malfunctions on the semiconductor device, and the most probable type or nature of the defect of the semiconductor device. To facilitate discussion and reporting, semiconductor device failures are often classified according to their electrical characteristics, commonly referred to as the failure mode. Typical classification of these modes include the following: single cell defect, adjacent cell defect, row failure, column failure, address failure, open pin, supply leakage, pin leakage, standby current leakage, and entire array failure (all dead cells).
In anticipation that some semiconductor devices will have defects, many semiconductor devices are designed with redundancies. In such semiconductor devices, a defective section of the semiconductor devices may be shut off and a redundant but properly operating section activated and used in place of the defective section. For example, typical integrated memory circuits include arrays of memory cells arranged in rows and columns. In many such integrated memory arrays, several redundant rows and columns are provided to be used as substitutes for defective rows or columns of memory. When a defective row or column is identified in the array, rather than treating the entire array as defective, a redundant row or column is substituted for the defective row or column. This substitution is performed by assigning the address of the defective row or column in the array to the redundant row or column such that, when an address signal corresponding to the defective row or column is received, the redundant row or column is addressed instead.
To make the substitution of the redundant row or column in the array substantially transparent to an operating system employing the memory circuit, the memory circuit may include an address detection circuit. The address detection circuit monitors the row and column addresses and, when the address of a defective row or column is received, enables or substitutes the redundant row or column in the array for the defective row or column.
One type of address detection circuit for memory-type semiconductor devices is a fuse-bank address detection circuit. Fuse-bank address detection circuits employ a bank of sense lines where each sense line corresponds to a bit of an address in the array of memory circuits. The sense lines are programmed by blowing fuses in the sense lines in a pattern corresponding to the address of the defective row or column in the array of memory circuits. Addresses are then detected by first applying a test voltage across the bank of sense lines. Then, bits of the address are applied to the sense lines. If the pattern of blown fuses precisely corresponds to the pattern of address bits, the sense lines all block current and the voltage across the bank remains high. Otherwise, at least one sense line is conductive and the voltage falls. Thus, a high voltage indicates the programmed address has been detected while a low voltage indicates a different address has been applied.
Antifuses have been used in place of conventional fuses. Antifuses are capacitive-type structures that, in their unblown states, form open circuits. Antifuses may be xe2x80x9cblownxe2x80x9d by applying a high voltage across the antifuse. The high voltage causes the capacitive-type structure to break down, thereby forming a conductive path through the antifuse.
Failures detected during a test of a semiconductor device may be caused by an actual failure in the semiconductor device or through a failure in the test system or through an environmental cause. If there is an actual failure of the semiconductor device, it is typically most efficient to repair the tested semiconductor device, if possible, rather than retest the semiconductor device (which may be very time consuming). On the other hand, if the failure is due to the test system or an environmental cause, the identification of failures will not be accurate and repair will not be an efficient use of resources.
Accordingly, there is a need for a system and method that determines whether it is more efficient to repair or retest a semiconductor device when failures are detected in testing.
The present invention relates to a system and method for testing a semiconductor device. The semiconductor device may be any of a variety of devices, including, but not limited to, a chip on a wafer, a bare chip off a wafer, a packaged chip including a package and leads. The chip may perform any of a variety of functions including, but not limited to, memory, microprocessor, and ASIC functions. Further, the system and method may involve testing more than one semiconductor device at a time.
A handler or prober may include a support that supports the semiconductor device and a regulated chamber. The support may be stationary or mobile. It may slide or rotate in and out of one or more regulated chambers (that regulate heat and perhaps also moisture). The support may support only one or more than one semiconductor device to be tested.
Test equipment, such as automated test equipment, performs tests on the semiconductor device. Under one embodiment, the test equipment includes probes that contact, for example, pads on the semiconductor device. In another embodiment, the support includes sockets that receive leads of the semiconductor device, and the test equipment makes electrical contact with the sockets to allow testing. The invention is not limited to sockets or probes, but may include any of various other means of making electrical contact. A testing controller may control the test equipment and regulated chamber.
Repair functions may be performed by the test equipment, adjacent repair equipment, or a remote test station.
A system controller may control the testing controller and the repair functions.
The test equipment may perform tests of a first type on the semiconductor device to identify failures in the semiconductor device, if any. A determination of the number of identified failures may be made by processing circuitry, which may be included in the system controller, testing controller, test equipment, or elsewhere. Decision circuitry may designate the semiconductor device as being ready for an additional procedure if, for example, the number of the identified failures is within a first number set. The decision circuitry may designate the semiconductor device for repair if, for example, the number of the identified failures is within a second number set. The decision circuitry may designate the semiconductor device for additional tests of the first type if, for example, the number of the identified failures is within a third number set. In an alternative embodiment, there could be another number set that divides one of the other number sets or a combination of them. Merely as examples, the tests of a first type may be a hot sort procedure and the additional tests may be a cold final procedure. The invention may be implemented with other procedures.
The decision circuitry may be included in the system controller, the testing controller, test equipment, or a combination of them, or elsewhere. The decision circuitry may use a fail bit counter in, for example, a backend test flow. Based on the number of bits in the semiconductor device that failed during the flow, the probability of repairing the part can be calculated. The semiconductor device may be binned differently, depending on the number of identified failures.
The decision circuitry may identify failures in the semiconductor device and determine a total number of identified failures, if any, in which the failures may be classified by class and number of identified failures for each class is determined, and wherein the total number of identified failures equals a sum of the identified failures for each class. In such a case, the decision circuitry may designate the semiconductor device as being ready for an additional procedure, designate the semiconductor device for repair, or designate the semiconductor device for additional tests of the first type, depending on a combination of the total number of identified failures and the number of identified failures in at least one of the classes
The decision circuitry may detect certain defects in the semiconductor device which are not classified as examples of the failures and, therefore, do not contribute to the number of identified failures.
In the case in which the decision circuitry designates the semiconductor device for repair, the decision circuitry may determine whether the semiconductor device is repairable and, if it is, a repair station may repair the semiconductor device.
Under one embodiment of the invention, the semiconductor device is rejected, junked or discarded if the number of the identified failures is within the second number set, but it is determined that the semiconductor device is not repairable.
The number sets are not restricted to any particular values but may include, for example, a signal number, a series of integers, or a range of numbers. There may be gaps between the number sets. In one embodiment, the first number set includes only zero, the second number set includes numbers greater than zero and less than a threshold, and the third number set includes numbers equal to or greater than the threshold. Although in a preferred embodiment each failure causes the number of failures to increment by one, the system or method could work by incrementing with values less than one or in negative numbers, or by decrementing. Different classes of failures could cause different values of incrementing or decrementing.
The tests of the first type may include subjecting the semiconductor device to various temperatures in a first range while monitoring electrical signals on the semiconductor device and in which the additional procedure includes subjecting the semiconductor device to various temperatures in a second range while monitoring electrical signals on the semiconductor device. There may be an overlap between the first and second ranges, or there may be no overlap between the ranges.
The tests of the first type and the additional tests of the first type may differ in some detail, although both may be of the first type, or may be identical.
In the additional tests of the first type, failures in the semiconductor device may be re-identified and a number of re-identified failures may be determined, and subsequently, the decision circuitry may designate the semiconductor device as being ready for the additional procedure if, for example, the number of the re-identified failures is within a fourth number set, the decision circuitry may designate the semiconductor device for repair if, for example, the number of the re-identified failures is within a fifth number set, and the decision circuitry may designate the semiconductor device for additional tests of the first type on the semiconductor device if, for example, the number of the re-identified failures is within a sixth number set. The decision circuitry may repeat these functions until the number of the re-identified failures is within the fourth number set, the semiconductor device is repairable and the number of the re-identified failures is within the fifth number set, or the additional tests of the first type have been performed a predetermined number of times and the number of re-identified failures is within the sixth number set (in which case the semiconductor device may be repaired, junked, or discarded). The fourth, fifth, and sixth number sets may be identical to or differ from the first, second, and third number sets, respectively. The values of the fifth and sixth number sets may change or remain constant as the functions are repeated.
In the additional procedure, the decision circuitry may designate the semiconductor device for tests of a second type to re-identify failures in the semiconductor device and determine a number of re-identified failures, if any. In such a case, the decision circuitry may designate the semiconductor device as being ready for a further procedure if, for example, the number of the re-identified failures is within a seventh number set; the decision circuitry may designate the semiconductor device for repair if, for example, the number of the re-identified failures is within an eighth number set; and the decision circuitry may designate the semiconductor device for additional tests of the second type if, for example, the number of the identified failures is within a ninth number set. The seventh, eighth, and ninth number sets may be identical to the first, second, and third number sets, respectively, or some other values.
The decision circuitry may designate the semiconductor device for repair if the number of the total identified failures is within a second number set, and the number of identified failures in a particular class is not within an auxiliary number set; and the decision circuitry may designate the semiconductor device for additional tests of the first type if either the total number of the identified failures is within a third number set or the number of identified failures in a particular class is within the auxiliary number set.
The decision circuitry may include dedicated hardware without software, circuitry that runs software (or firmware), such as a microprocessor, or some combination of them, or some other circuitry that may make decisions based on inputs.
The system may include wireless transmission of information.